The present invention relates to a system for forming test patterns for a large scale integrated circuit (LSI) included in a logic circuit and, more particularly, to a system for forming test patterns for a target LSI on the basis of logic simulation results of an overall logic circuit.
In a system for testing the functions and the like of LSIs, a large number of test patterns must be prepared on the basis of combinations of the state values of input pins and the state values of corresponding output pins which are obtained when an LSI as a test target is in a normal state. Various types of systems for forming test patterns for an LSI have been known. According to one of these systems, test patterns for a target LSI are formed on the basis of results of logic simulation of an overall logic circuit which is executed when, e.g., design of a logic circuit including the LSI is completed. In such a conventional system for forming test patterns for an LSI, after input/output pins of a target LSI (for which test patterns are to be formed) in a logic circuit are designated, simulation input patterns are input to perform the logic simulation of the overall logic circuit. In the process of the logic simulation, data of the state values of the designated input/output pins which corresponds to all the clocks of the simulation input patterns are acquired in units of clocks. The acquired data are then converted into test patterns.
An advantage of the above-described conventional system for forming test patterns for an LSI is that test patterns for a target LSI can be obtained by using logic simulation results of a logic circuit.
When each of the LSIs in a logic circuit is taken into consideration, the following point should be noted. It is rare for a given LSI to be always operated during an operation of the logic circuit, and the period during which it is not operated is long. In the above-described conventional system for forming test patterns for an LSI, however, data of the state values of the input/output pins of a target LSI is acquired for all the clocks of simulation input patterns to a logic circuit. That is, useless data is also acquired, i.e., data acquired when the target LSI is not operated. This poses a problem in terms of efficiency of formation of test patterns.